The subject matter of this invention pertains to computing systems, and more particularly, to a store queue in a first level of memory hierarchy and a store queue and write buffers in a second level of cache memory hierarchy of a multiprocessor computer system for queuing data intended for storage in the second level of cache memory hierarchy.
Computing systems include multiprocessor systems. Multiprocessor systems comprise a plurality of processors, each of which may at some point in time require access to main memory. This requirement may arise simultaneously with respect to two or more of the processors in the multiprocessing system. Such systems may comprise intermediate level caches for temporarily storing instructions and data. For example, U.S. Pat. Nos. 4,445,174 and 4,442,487 disclose multiprocessor systems including intermediate first level cache storage (L1 cache) and intermediate second level cache storage (L2 cache). These patents do not specifically disclose a system configuration which comprises an Ll cache for each processor of the multiprocessor system, an L2 cache connected to and shared by the individual L1 caches of each processor, and a main memory, designated L3, connected solely to the shared L2 cache. In such a configuration, if data and/or instructions, stored in an L1 cache of one processor of the multiprocessor system, should be moved for storage into the shared L2 cache, and ultimately into L3, and if the shared L2 cache is busy storing data and/or instructions associated with another of the processors of the multiprocessor system, the L1 cache of the one processor must wait until the shared L2 cache is no longer busy before it may begin its storage operations. Therefore, a queuing system is needed, for connection between the individual L1 caches of each processor and the shared L2 cache, to queue the data and/or instructions from the L1 cache of the one processor prior to storage in the shared L2 cache so that the one processor may begin another operation. In such a queuing system, when a first set of data and/or instructions are stored in the queue, the queue itself may be full; therefore, when the one processor intends to store a second set of data and/or instructions in the queue, as well as in its L1 cache, since the queue is full, the one processor cannot begin another operation until the queue is no longer full. Therefore, it is desirable that the queue be designed in stages, in a pipelined manner, such that the second set of data and/or instructions may be queued along with the first set of data and/or instructions. In this manner, multiple sets of data and/or instructions, intended for storage in an L1 cache, may be queued for ultimate storage in the shared L2 cache, thereby permitting continued operation of the one processor associated with the L1 cache.
In addition, when data is modified by one processor of a multiprocessor configuration, which includes a plurality of processors, a single main memory, and intermediate level caches L1 and L2, if the corresponding un-modified data is stored in the processor's cache, the modified data must be re-stored in the processor's cache. The modified data must be re-stored in its cache before the other processors may "see" the modified data. Therefore, some method of policing the visibility of the modified data vis-a-vis the other processors in the multiprocessor configuration is required. Furthermore, an apparatus is needed to maintain accurate control over access to main memory and the caches. In this application, the apparatus for policing the visibility of the modified data vis-a-vis other processors and for maintaining control over access to the main memory and the caches is termed a "Storage Subsystem".